The present invention relates to a semiconductor memory device having a large storage capacity and fast operational performance, and particularly to a semiconductor static memory device having a storage capacity as large as 16M bits or more which is still capable of operating fast.
For accomplishing a fast, high storage capacity semiconductor memory device, circuitry is known which operates on a large-capacity semiconductor static memory device to achieve the fast operation, as described in an article by Hirose et al. entitled "A 20ns 4Mb CMOS SRAM with Hierarchical Word Decoding Architecture" published in the ISSCC 90 Digest of Technical Papers, Vol. 33 (IEEE, 1990), pp. 132-133, for example. This prior art is pertinent to a 4M-bit semiconductor static memory device.
The above-mentioned conventional 4M-bit memory device has a structure of memory cell array of 1024 rows by 4096 columns on a chip. In case the device has only one row decoder, the number of column address lines for each row is large, i.e., 4096 lines, and resulting long word lines which are formed of polysilicon having a large resistance will incur an increased delay time. In dealing with this matter, the above-mentioned conventional memory device is designed to divide memory cells into a plurality of cell arrays so as to reduce the length of word lines formed of polysilicon, thereby preventing the increase of delay time.
In this memory device, each cell array is provided with a local row decoder which performs a logical AND operation between the cell array select signal and the global word lines passing through a memory cell which is selected by a row decoder, and a word line is selected by the output of the local row decoder. The device necessitates local row decoders equal in number to the cell arrays, resulting in an increased chip area needed for the local row decoders.
A static RAM of 4M bits or more consists of a large number of memory cells inherently, and therefore it will not fit in a standard package if the chip area increases excessively. On this account, the number of divisions of memory cells must be reduced to minimize the increase of chip area, and therefore the reduction in the length of word lines is limited and an increased delay time cannot be avoided.